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Resume
I am an an associate professor at INSA Rennes, with a joint appointment at the IETR laboratory. My current research efforts concentrates on compilation for MPSoC and FPGA. I am interested in embedded systems programming, compilation and hardware architecture.
I received the Engineering and Master degrees in Electrical Engineering from Polytech’Orléans, France, in 2011, and the Ph.D. degree in Computer Science from INSA Lyon, France, in 2014, working with the CITI-Inria laboratory in collaboration with CEA LETI. I previously worked at Nokia in Berkeley, California, National Instruments in Austin, Texas and IRISA laboratory in Rennes, France.
Selected Publications
For a full list of publications, see publications.
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Quentin Milot, Mickaël Dardaillon, Justine Bonnot, Daniel Ménard, “Wordlength Optimization for Custom Floating-point Systems”, in Conference on Design & Architectures for Signal & Image Processing (DASIP), Munich, Germany, Jan. 2024.
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Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan, “Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis Workflow”, in ACM Transactions on Reconfigurable Technology and Systems (TRETS), Sep. 2023.
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Karol Desnos, Thomas Bourgoin, Mickaël Dardaillon, Nicolas Sourbier, Olivier Gesny, Maxime Pelcat, “Ultra-Fast Machine Learning Inference through C Code Generation for Tangled Program Graphs”, in IEEE Workshop on Signal Processing Systems (SiPS), Rennes, France, Nov. 2022.
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Pedro Ciambra, Mickaël Dardaillon, Maxime Pelcat, Hervé Yviquel, “Co-optimizing Dataflow Graphs and Actors with MLIR”, in IEEE Workshop on Signal Processing Systems (SiPS), Rennes, France, Nov. 2022.
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Mickaël Dardaillon, Stefanos Skalistis, Isabelle Puaut, Steven Derrien, “Reconciling Compiler Optimizations and WCET Estimation Using Iterative Compilation”, in Real Time Systems Symposium (RTSS), Hong Kong, China, Dec. 2019.
Miscellaneous
Most of my free time is spent outside, either high up in the mountains or deep down freediving, and I usually carry a camera: